{"dataType": "CVE_RECORD", "cveMetadata": {"state": "PUBLISHED", "cveId": "CVE-2025-51677", "assignerOrgId": "8254265b-2729-46b6-b9e3-3dfca2d5bfca", "assignerShortName": "mitre", "dateUpdated": "2026-07-17T19:43:37.589Z", "dateReserved": "2025-06-16T00:00:00.000Z", "datePublished": "2026-07-17T00:00:00.000Z"}, "containers": {"cna": {"providerMetadata": {"orgId": "8254265b-2729-46b6-b9e3-3dfca2d5bfca", "shortName": "mitre", "dateUpdated": "2026-07-17T19:43:37.589Z"}, "descriptions": [{"lang": "en", "value": "An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior."}], "affected": [{"vendor": "n/a", "product": "n/a", "versions": [{"version": "n/a", "status": "affected"}]}], "references": [{"url": "https://github.com/openrisc/mor1kx/issues/160#issuecomment-2585618940"}, {"url": "https://www.arxiv.org/abs/2504.18812"}, {"url": "https://mason.gmu.edu/~rsaravan/projects/synfuzz/cve/cve.html"}], "problemTypes": [{"descriptions": [{"type": "text", "lang": "en", "description": "n/a"}]}]}}, "dataVersion": "5.2"}

{}

{}

{}

{"affected": [{"configurations": [{"platform": null, "status": "affected", "versions": {"scheme": "generic", "value": "83ac6b"}}], "enrichment": {"confidence": 90.0, "confidence_source": "inferred", "scores": [{"score": 90.0, "source": "inferred"}, {"score": 100.0, "source": "matching"}]}, "original": {"product": "n/a", "source": "cna", "vendor": "n/a"}, "product": "or1200", "vendor": "openrisc"}], "created": "2026-07-17T22:00:04.378869+00:00", "updated": "2026-07-17T22:00:04.378889+00:00", "vendors": ["openrisc", "openrisc$PRODUCT$or1200"]}