The Intel EPT paging code uses an optimization to defer flushing of any cached
EPT state until the p2m lock is dropped, so that multiple modifications done
under the same locked region only issue a single flush.
Freeing of paging structures however is not deferred until the flushing is
done, and can result in freed pages transiently being present in cached state.
Such stale entries can point to memory ranges not owned by the guest, thus
allowing access to unintended memory regions.
Metrics
Affected Vendors & Products
References
History
Mon, 23 Mar 2026 08:30:00 +0000
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Mon, 23 Mar 2026 07:15:00 +0000
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| Description | The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions. | |
| Title | Use after free of paging structures in EPT | |
| References |
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Status: PUBLISHED
Assigner: XEN
Published:
Updated: 2026-03-23T07:32:25.539Z
Reserved: 2026-01-14T13:07:36.961Z
Link: CVE-2026-23554
No data.
Status : Received
Published: 2026-03-23T07:16:07.200
Modified: 2026-03-23T08:16:16.350
Link: CVE-2026-23554
No data.
OpenCVE Enrichment
No data.