An issue has been identified in Arm C1-Pro before r1p2-50eac0, where, under certain conditions, a TLBI+DSB might fail to ensure the completion of memory accesses related to SME.
History

Mon, 02 Mar 2026 17:15:00 +0000

Type Values Removed Values Added
Metrics cvssV3_1

{'score': 3.6, 'vector': 'CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:U/C:N/I:L/A:L'}

ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}


Mon, 02 Mar 2026 15:15:00 +0000

Type Values Removed Values Added
Description An issue has been identified in Arm C1-Pro before r1p2-50eac0, where, under certain conditions, a TLBI+DSB might fail to ensure the completion of memory accesses related to SME.
Weaknesses CWE-362
References

cve-icon MITRE

Status: PUBLISHED

Assigner: Arm

Published:

Updated: 2026-03-02T16:16:02.649Z

Reserved: 2026-01-15T15:26:49.754Z

Link: CVE-2026-0995

cve-icon Vulnrichment

Updated: 2026-03-02T16:15:31.160Z

cve-icon NVD

Status : Received

Published: 2026-03-02T15:16:31.910

Modified: 2026-03-02T17:16:29.030

Link: CVE-2026-0995

cve-icon Redhat

No data.

cve-icon OpenCVE Enrichment

No data.